Introduction:
Computer Organization:
Compuetr Organization is concerned with the way the hardware components operate and the
way they are connected together to form the computer system. The various components are
assumed to be in place and the task is to investigate the organizational structure to verify that the
computer parts operate as intended.
Computer Design:
Computer design is concerned with the hardware design of the computer. Once the computer
specifications are formulated it is the task of the designer to develop hardware for the system.
Computer design is concerned with the determination of what hardwareshould be used and how the
parts should be connected. This aspect of computer hardware is sometimes referred to as computer
implementation.
Computer Architecture:
Computer architecture is concerned with the structure and behavior of the ocmputer as seen
by the user. It includes the information formats, the instruction set and techniques for addressing
memory. The architectural design of a computer system is concerned with the specifications of the
various functional modules, such as processors and memories and structuring them together into a
computer system.
Register Transfer and Microoperation
Register:
A register is a group of flip-flops with each flip-flop capable of storing of information. An
n-bit register has a group of n flip-flops and is capable of storing any binary information of n bits. In
addition to the flip-flops, a register may have combinational gates that perform certain dataprocessing
tasks.
So a register consists of a group of flip-flops and gates that effect their transition. The flip
flops hold the binary information and the gates control when and how new information is
transferred into the register.
Microoperation:
· The operations executed on data stored in registers are called microoperations.
· A micro operation is an elementary operation performed on the information stored in
one or more registers.
· The result of the operation may replace the previous binary information of a register
or may be transferred to another register.
· A micro operation requires only one clock pulse for execution if the operation is done
in parallel.
· The micro operations most often encountered in digital computers are classified into 4
categories:
o Register Transfer Micro operations: transfer binary information from one
register to another.
o Arithmetic Micro Operations: Perform arithmetic operations on numeric data
stored in registers.
o Logic Micro Operations: Perform bit manipulation operations on non numeric
data stored in registers.
o Shift Micro operations: perform Shift operations on data stored in registers.
Examples of registers that implement microoperations:
1. Counter with parallel load is capable of performing the microoperations increment and load.
2. A bidirectional shift register is capable of performing the shift right and shift left micro
operations.
Register Transfer Language:
· The symbolic notation used to describe the micro operation transfers among registers is
called a register transfer language.
· It’s a convenient tool for describing the internal organization of digital computers in concise
and precise manner.
· It can also be used to facilitate the design process of digital systems.
· A language used to describe the operation of instructions within a processor. RTL describes
the requirements of data and control units in terms of digital logic to execute an assembly
language instruction. Each instruction from the architecture's instruction set is defined in
RTL.
· A kind of hardware description language (HDL) used in describing the registers of a
computer or digital electronic system, and the way in which data is transferred between
them.
· An intermediate code for a machine with an infinite number of registers, used for machineindependent
optimisation.
Register Transfer Micro operations:
Computer registers are designated by capital letters to denote the function of the register.
For Example:
MAR - Memory Address Register.
PC - Program Counter.
IR – Instruction Register.
R1 – Processor register.
The individual flip-flops in an n-bit register are numbered in sequence from 0 through n-1,
starting from 0 in the rightmost position and increasing the numbers toward the left.
The most common way to represent a register is by a rectangular box with the name of the
register inside.
Information transfer from one register to another is designated in symbolic form by means of
a replacement operator.
R2 ← R1
· Denotes a transfer of the content of register R1 into register R2. It designates a
replacement of the content of R2 by the content of R1.
· The content of the source register R1 does not change after the transfer.
· Register transfer implies that
o circuits are available from the outputs of the source register to the inputs of the
destination register.
o And that the destination register has a parallel load capability.
· The following table describes the basic symbols for register transfers:
Symbol Description Examples
Letters
(and numerals) Denotes a register MAR, IR, R5
Parentheses ( ) Denotes part of a register PC(0-7), R0(H)
Arrow ← Denotes transfer of information R2 ← R1
Separates control function from
micro operations
T: R2 ← R1
Comma , Separates two micro operations R2 ←R1, PC(L) ← R0(L)
Control Function:
· A control function is a boolean variable.
· It is used to initiate the sequence of operations
· When it is one binary state, it initiates an operation and when in other binary state, inhibits
the operation.
· The control function is included in the statement as follows:
P: R2 ←R1
o It symbolizes the requirement that the transfer operation be executed by the hardware
only if P=1.
o The control condition is terminated with a colon.
TRANSFER FROM REGISTER A TO B WHEN P=1
Bus and Memory Transfer
Bus:
A bus structure consists of a set of common lines, one for each bit of a register, through
which binary information is transferred one at a time.
Control signals determine which register is selected by the bus during each particular register
transfer.
Need for the Bus:
A typical digital computer has many register, and paths must be provided to transfer
information from one register to another.
The number of wires will be excessive if separate lines are used between each register and all
other registers in the system.
Hence common bus system is an efficient scheme for transferring information between
registers in a multiple register configuration.
Construction of bus system:
· One way of constructing a common bus system is with multiplexers.
· The number of multiplexers needed to construct the bus is equal to n, where n is the number of
bits in each register.
· The size of each multiplexers is k X 1 where k is the number of registers in the digital system.
o For example a common bus for eight registers of 16 bits each requires 16
multiplexers. Each multiplexer must have eight data input lines and three selection
lines to multiplex one significant bit in the eight registers.
Information transfer with Bus:
The transfer of information from a bus into one of many destination registers can be
accomplished by connecting the bus lines to the inputs of all destination registers and activating the
load control of the particular destination register selected.
When the bus is includes in the statement, the register transfer is symbolized as follows:
BUS ← C, R1 ← BUS
The content of register C is placed on the bus, and the content of the bus is loaded into
register R1 by activating its load control input.
If the bus is known to exist in the system, it may be convenient just to show the direct
transfer.
R1 ← C
From this statement the designer knows which control signals must be activated to produce
the transfer through the bus.
Three-State Bus Buffers:
Three-State Gate:
A three-state gate is a digital circuit that exhibits three staes. Two of the states are signals
equivalent to logic 1 and 0 as in conventional gate. The third state is a high impedance state. High
impedence state means that the output is disconnected and does not have a logic significance.
Three-State Buffer:
Three-state gates may perform any conventional logic, such as AND or NAND. However the
one most commonly used in the design of a bus system is the buffer gate.
· Three state buffer has a normal input and a control input.
· The control input determines the output state.
- When the control input is equal to 1, the output is enabled and it is equal to the normal
input.
- When the control input is 0, the output is disabled and the gate goes to a high-impedance
state regardless of the value in the normal input.
High Impedence if C=0
Control Input C
Graphic symbol for three-state buffer
Construction of Bus System with three state buffers:
· The outputs of the three state buffers are connected together to form a single bus line.
· The control inputs to the buffers determine which of the normal inputs will communicate
with the bus line.
· The connected buffers must be controlled so that only one three-state buffer has access to the
bus line while all other buffers are maintained in a high impedance state.
o One way to ensure that no more than one control input is active at any given time
is to use a decoder.
o When the enable input of the decoder is 0, all of its four outputs are 0, and the bus
line is in a high-impedence state because all four buffers are disabled.
o When the enable input is active, one of the three-state buffers will be active,
depending on the binary value in the select inputs of the decoder.
D0
select
lines
Enable
Bus Line with three state buffers
Memory Transfer
Read Operation:
The transfer of information from a memory word to the outside environment is called a read
operation.
A0
B0
C0
D0
Bus line for bit 0
0
S1
1
S0 2X4
Decoder 2
E
3
Write Operation:
The transfer of new information to be stored into the memory is called a write operation.
Memory Transfer:
· A memory word will be symbolized by the letter M.
· The particular memory word among the many available is selected by the memory address
during the transfer.
· It is necessary to specify the address of M when writing memory transfer operations. This
will be done by enclosing the address in square brackets following the letter M
Example:
Consider a memory unit that receives the address from a register called the address register,
symbolized by AR. The data are transferred to another register, called the data register, symbolized
by DR.
The read operation can be stated as follows:
Read: DR ← M[AR]
This causes a transfer of information into DR from memory word selected by the address in
AR.
Write: M[AR] ← R1
This causes a transfer of information from R1 into the Memory word M selected by the
address in AR.
A rithmetic Micro operat io ns:
The basic arithmetic microoperations are addition, subtraction, increment, decrement and
arithmetic shift.
The arithmetic operation defined by the statement
R3 ← R1 + R2
Specifies an add operation. It states that the contents of register R1 are added to the contents
of register R2 and the sum transferred to register R3. To implement this statement with hardware
we need three registers and the digital component the performs the addition operation.
The basic arithmetic operations are listed in the table below:
Symbolic
Designation
Description
R3 ← R1 + R2 Contents of R1 plus R2 transferred to R3
R3 ← R1 – R2 Contents of R1 minus R2 transferred to R3
R2 ← R2’ One’s complement of the contents of R2
R2 ← R2’ + 1 Two’s complement of the contents of R2 (Negate)
R3 ← R1 + R2’ +1 R1 plus the 2’s complement of R2 (Subtraction)
R1 ← R1 +1 Increment the contents of R1 by one
R1 ← R1 – 1 Decrement the contents of R1 by one
Note: Division and multiplication are valid arithmetic operations but they are not included in the
basic set of micro operations. Because in most computers, the multiplication operation is
implemented with a sequence of add and shift micro operations and division is implemented with a
sequence of subtract and shift micro operations. To specify the hardware in such a case requires a
list of statements that use the basic micro operations add, subtract and shift.
Hardware for implementing the arithmetic micro operations:
Binary Adder: (For Addition)
· The digital circuit that forms the arithmetic sum of two bits and a previous carry is called a
full-adder.
· The digital circuit that generates the arithmetic sum of two binary numbers of any length is
called a binary adder.
· The binary adder is constructed with full-adder circuits connected in cascade, with the output
carry from one full-adder connected to the input carry of the next full adder.
· An n-bit binary adder requires n full adders. The output carry from each full-adder is
connected to the imput carry of the next-high-order full-adder.
4 - Bit Binary Adder
An n-bit binary adder requires n full-adders.
The output carry from each full-adder is connected to the input carry of the next-high-order
full-adder.
The n bits for A input come from one register and the n data bits for the B input come from
another register.
The sum can be transferred to a third register or to one of the source registers replacing its
previous content.
Binary Adder – Subtractor:
Subtraction:
The subtraction of binary numbers can be done by means of complements.
One’s complement can be implemented with inverters.
1 can be added to the sum through the input carry.
Adder-Subtractor:
The addition and subtraction operations can be combined into one common circuit by
including an exclusive-OR gate with each full adder.
C2
FA C3 C1 C0
B3 A3 B2 A2 B1 A1 B0 A0
FA FA FA
C4 S3 S2 S1 S0
Binary Incrementer:
The increment microoperation adds one to a number in a register.
This operation can be easily implemented with a binary counter.
Every time the count enable is active, the clock pulse transition increments the content of the
register by one.
There may be occasions when the increment microoperation must be done with a
combinational circuit independent of a particular register. This can be accomplished by means of
half-adders.
4 – bit binary incrementer using Half Adders
Arithmetic Circuit:
· The arithmetic microoperations can be implemented in one composite arithmetic circuit.
· The basic component of an arithmetic circuit is the parallel adder.
C4 S3 S2 S1 S0
x y
HA
C S
x y
HA
C S
x y
HA
C S
x y
HA
C S
A3 A2 A1 A0 1
· By controlling the data inputs to the adder, it is possible to obtain different types of
arithmetic operations.
Logic Micro operations:
· Logic Micro operations specify binary operations for strings of bits stored in registers.
· These operations consider each bit of the register separately and treat them as binary
variables.
· Logic micro operations are useful for bit manipulation of binary data and for making logical
decisions. They are useful for manipulating individual bits or a portion of a word stored in a
register. They can be used to change bit values, delete a group of bits or insert new bit values
into the register.
· The complement micro operation is the same as 1’s complement and uses bar on top of the
symbol that denotes the register name.
· The symbol is used to denote an OR micro operation will be used to denote AND
micro operation.
· There are 16 different logic operations that can be performed with two binary variables.
Example:
P+Q: R1← R2 + R3, R4← R5 R6
The + between P and Q is an OR operation between two binary variables of a control function. The
+ between R2 and R3 specifies an add micro operation. The OR microoperation is designated by the
symbol between registers R5 and R6.
Hardware Implementation:
· The hardware implementation of logic micro operations requires that logic gates be
inserted for each bit or pair of bits in the registers to perform the required logic function.
· Although there are 16 logic micro operations, most computers use only four – AND, OR,
XOR and complement – from which all others can be derived.
· The following figure shows one stage of a circuit that generates the four basic logic micro
operations:
4 X 1
MUX
1
2
3
4
S1
S2
Ai
Bi
Ei
.
One stage logic circuit
Shift Micro Operations:
· Shift Micro operations are used for serial transfer of data.
· The contents of the register can be shifted to the left or right.
· The first flip flop receives the serial input and at the same time bits in the register are shifted.
o During the shift left operation the serial input transfers a bit into the rightmost
position.
o During a shift right operation the serial input transfers a bit into the leftmost position.
· There are three types of shifts: logical, circular, and arithmetic
· The information transferred through the serial input determines the type of shift.
Logical shift:
A logical shift is one that transfers 0 through the serial input. The bit transferred to the end
position through the serial input is assumed to be 0 during logical shift.
Logical shift left:
Circular Shift (Rotate operation):
The circular shift circulates the bits of the register around the two ends without loss of
information. This is accomplished by connecting the serial output of the shift register to its serial
input.
Rotate Left:
Rotate right:
Arithmetic Shift:
· An arithmetic shift is a microoperation that shifts a signed binary number to the left or right.
· An arithmetic shift left multiplies a signed binary number by 2.
o An arithmetic shift left inserts a 0 into LSB and shifts all other bits.
· An arithmetic shift right divides the number by 2.
o The arithmetic shift right leaves the sign bit unchanged and shifts the number including
the sign bit to the right and the bit in LSB position is lost.
· An overflow occurs after an arithmetic shift left if initially, before the shift , Rn-1 is not equal to
Rn-2. An overflow flip flop Vs can be used to detect an arithmetic shift-left overflow.
Vs = Rn-1 XOR Rn-2
If Vs =0 there is no overflow, but if Vs=1, there is an overflow and a sign reversal after the shift.
Hardware Implementation:
Shift Unit with a Bidirectional Shift Register:
A shift unit can be constructed using a bidirectional shift register with parallel load.
Information can be transferred to the register in parallel and then shifted to the right or left. In this
type of configuration, a clock pulse is needed for loading the data into the register, and another
pulse is needed to initiate the shift. In a processor unit with many registers it is more efficient to
implement the shift operation with a combinational circuit. In this way the content of a register that
has to be shifted is first placed onto a common bus whose output is connected to the combinational
shifter, and the shifted number is then loaded back into the register. This requires only one clock
pulse for loading the shifted value into the register.
Shift Unit with combinational circuit (Shifter):
A combinational circuit shifter can be constructed with multiplexers. The 4 bit shifter has
four data inputs, A0 through A3, and four data outputs H0 through H3. There are two serial inputs,
one for shift left and the other for shift right. When the selection input S=0, the input data are
shifted right. When S=1, the input data are shifted left.
A shifter with n data inputs and outputs requires n multiplexers. The two serial inputs can be
controlled by another multiplexer to provide the three possible types of shifts.
Function Table
Select Output
0 IR A0 A1 A2
1 A1 A2 A3 IL
A0
A1
A2
A3 S
MUX
01
S
MUX
01
Serial Input (IL)
S
MUX
01
Serial Input (IR)
Select 0 for shift right
1 for shift left
S
MUX
01
H0
H1
H2
H3
Arithmetic Logic Shift Unit:
ALU:
Instead of having individual registers performing the micro operations directly computer
systems employ a number of storage registers connected to a common operational nit called an
arithmetic logic unit.
· To perform a micro operation, the contents of specified registers are placed in the inputs of the
common ALU.
· ALU performs the operation.
· The result of the operation is then transferred to a destination register.
· The ALU is a combinational circuit so that the entire register transfer operation from the source
registers through the ALU and into the destination register can be performed during one clock
pulse period.
· The shift micro operations are often performed in a separate unit, but sometimes the shift unit is
made part of the overall ALU.
· The arithmetic, logic, and shift circuits can be combined into one ALU with common selection
variables.
Bi
Ai
Ai-1
Ai+1
Ei
Di
Fi
shr
shl
S3
S2
S1
S0
Ci+1
One stage
of
arithmetic
circuit
One stage
of
logic
circuit
Select
0 4 X 1
1 MUX
2
3
Ci
One Stage of Arithmetic Logic Shift Unit
*****************
Basic Computer Organization and Design
Instruction Codes:
· An instruction code is a group of bits that instruct the computer to perform a specific operation.
· It is usually divided into parts, each having its own particular interpretation.
· The most basic part of an instruction code is its operation part.
o The operation part of an instruction code specifies the operation to be performed.
o The operation code of an instruction is a group of bits that define such operations as add,
subtract, multiply, shift and complement.
o The number of bits required for the operation code of an instruction depends on the total
number of operations available in the computer.
o The operation code must consist of at least n bits for a given 2n (or less) distinct
operations.
· An instruction code must also specify the memory words where the operands are to be found, as
well as the register or memory word where the result is to be stored.
o Memory words can be specified in the instruction codes by their address.
o Processor registers can be specified by assigning to the instruction another binary code of
k bits that specifies one of 2k registers.
· There are many variations for arranging the binary code of instructions, and each computer has
its own particular instruction code format.
Stored Program Organization:
· The simplest way to organize a computer is to have one processor register and an instruction
code format with two parts.
o The first part specifies the operation to be performed.
o Second part specifies an address. The memory address tells the control where to find
an operand in memory.
· Instructions are stored in one section of memory and data in another.
o For a memory unit with 4096 words we need 12 bits to specify an address since
212=4096.
o If we store each instruction code in one 16 bit memory word, then 12 bits are used for
specifying the address and 4 bits for the operation code to specify one out of 16
possible operations.
· The control reads a 16-bit instruction from the program portion of memory, it uses the 12-bit
address part of the instruction to read a 16-bit operand from the data portion of the memory.
It then executes the operation specified by the operation code.
· If an operation in an instruction code does not need an operand from memory, the rest of the
bits in the instruction can be used for other purposes.
o For example, operations such as clear AC, Complement AC and Increment AC
operate on data stored in the AC register. They do not need an operand from memory.
For these types of operations, the second part of the instruction code is not needed for
specifying a memory address and can be used to specify other operations for the
computer.
Immediate instruction:
· It is sometimes convenient to use the address bits of an instruction code not as an address but
as the actual operand.
· When the second part of an instruction code specifies an operand, the instruction is said to
have an immediate operand.
Direct address:
When the second part specifies the address of an operand, the instruction is said to have a direct
address.
Indirect Address:
· In indirect addressing mode, the bits in the second part of the instruction designate an address of
a memory word in which the address of the operand is found.
· One bit of the instruction code (mode bit) can be used to distinguish between a direct and an
indirect address.
o Mode bit is 0 for direct address and 1 for indirect address.
· The indirect address instruction needs two references to memory to fetch an operand.
o The first reference is needed to read the address of the operand
o The second is for the operand itself.
Effective Address:
Effective address is the address of the operand in a computation-type instruction or the target
address in a branch-type instruction.
· The memory word that holds the address of the operand in an indirect address instruction is used
as a pointer to an array of data.
Computer registers:
Accumulator:
The accumulator is a general purpose processing register.
Instruction register:
The instruction read from memory is placed in the instruction register (IR).
Temporary Register:
The temporary register (TR) is used for holding temporary data during the processing.
Memory address register:
The memory address register (AR) holds the address for memory.
Data register:
The data register holds the operand read from the memory.
Program Counter:
· Program Counter (PC) is register that holds the address of the next instruction to be read from
memory after the current instruction is executed.
· The PC goes through a counting sequence and causes the computer to read sequential
instructions previously stored in memory.
· In case of branch instruction the address part of the branch instruction is transferred to PC to
become the address of the next instruction.
· To read an instruction, the content of PC is taken as the address for memory and a memory read
cycle is initiated. PC is then incremented by one, so it holds the address of the next instruction in
sequence.
· Number of bits in the PC is equivalent to the width of a memory address.
INPR:
This register is used for input. The input register receives an 8-bit character from an input device.
OUTR:
This register is used for output. The output register hold an 8-bit character for an output device.
Basic Computer Registers and memory
Common Bus System:
The basic computer has eight registers, a memory unit, and a control unit. Paths must be
provided to transfer information from one register to another and between memory and register. The
number of wires will be excessive if connections are made between the outputs of each register and
the inputs of the other register. A more efficient scheme for transferring information in a system
with many registers is to use a common bus.
7 0 7 0
11 0
PC
15 0
IR
15 0
TR
OUTR INPR
Memory
4096 words
16 bits per word
AR
11 0
15 0
AC
15 0
DR
· The outputs of seven registers and memory are connected to the common bus.
· The specific output that is selected for the bus lines at any given time is determined from the
binary value of the selection variables S2, S1 and S0.
· The lines from the common bus are connected to the inputs of each register and the data inputs
of the memory.
· The particular register whose LD (Load) input is enabled receives the data from the bus during
the next clock pulse transition.
· The memory receives the contents of the bus when its write input is activated. The memory
places its 16-bit output onto the bus when the read input is activated and S2S1S0=111.
Computer Instructions:
Instruction Format:
Memory Unit
4096 X 16
· The basic computer has three instruction code formats. Each format has 16 bits. The type of
the instruction is recognized by the computer control from the four bits in positions 12 through
15 of the instruction.
· The operation code(opcode) part of the instruction contains three bits and the meaning of
remaining 13 bits depends on the operation code encountered.
· In memory reference instructions the opcode not equal to 111 and they use 12 bits to specify
an address and one bit to specify the addressing mode I.
o I is equal to 0 for direct address and 1 for indirect address.
· Register reference instructions are recognized by the opcode 111 with a 0 in the leftmost bit of
the instruction.
o A register-reference instruction specifies an operation on or a test of the AC register.
o An operand from the memory is not needed. Therefore the other 12 bits are used to
specify the operation or test to be executed.
· An input-output instruction does not need a reference to memory and is recognized by the
opcode 111 with a 1 in the leftmost bit of the instruction.
o The remaining 12 bits are used to specify the type of input-output operation or test to be
performed.
The instructions for the basic computer are listed below:
15 14 12 11 0
Opcode Address
Memory-reference Instruction
I (Opcode = 000 through 110)
15 12 11 0
0 1 1 1 Register transfer Operation
Register- reference Instruction
(Opcode = 111 I = 0)
15 12 11 0
1 1 1 1 I/O Operation
Input-output instruction
(Opcode = 111 I=1)
Instruction set completeness:
A computer should have a set of instructions so that the user can construct machine language
programs to evaluate any function that is known to be computable. The set of instructions are said
to be complete if the computer includes a sufficient number of instructions in each of the following
categories:
1. Arithmetic, logical and shift instructions: These instructions provide computational
capabilities for processing the type of data that the user may wish to employ.
2. Instructions for moving information to and from memory and processor registers: the
bulk of the binary information in a digital computer is stored in memory, but all the
computations are done in processor registers. Therefore, the user must have the capability of
moving information between these two units.
3. Program control instructions together with instructions that check status conditions:
Decision making capabilities are an important aspect of digital computers. Program control
instructions such as branch instructions are used to change the sequence in which the
program is executed.
4. Input and output instructions: these instructions are needed for communication between
the computer and the user. Programs and data must be transferred into memory and results of
computations must be transferred back to the user.
Timing and control:
· The timing for all registers in the basic computer is controlled by a master clock generator.
· The clock pulses do not change the state of a register unless the register is enabled by a control
signal.o The control signals are generated in the control unit and provide control inputs for the
multiplexers in the common buts, control inputs in processor registers, and micro
operations for the accumulator.
o There are two major types of control organization:
i. Hardwired control: in hardwired organization, the control logic is
implemented with gates, flip-flops, decoders, and other digital circuits.
ii. Microprogrammed control: in this organization, the control information is
stored in a control memory. The control memory is programmed to initiate the
required sequence of microoperations.
Control Unit of a basic computer
Control
Logic
Gates
15 14 … 2 1 0
4 X 16
Decoder
4 – bit
Sequence
Counter
Instruction Register (IR)
14 13 12
3X8
Decoder
7 6 5 4 3 2 1 0
I
15 11-0
Increment (INR)
Clear (CLR)
Clock
Instruction Cycle:
· The program residing in the memory is executed in the computer by going through a cycle for
each instruction.
· Each instruction cycle in turn is subdivided into a sequence of subcycles or phases.
· In the basic computer each instruction cycle consists of the following phases:
o Fetch an instruction from memory
o Decode the instruction
o Read the effective address from memory if the instruction has an indirect address.
o Execute the instruction.
· Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the
next instruction.
· This process continues until HALT instruction is encountered.
Fetch and Decode:
1. Program counter is loaded with the address of the first instruction in the program.
2. The sequence counter is cleared to 0, providing a decoded timing signal T0.
3. After each clock pulse, SC is incremented by one, so that the timing signals go through a
sequence T0, T1, T2 and so on.
4. The micro operations for the fetch and decode phases can be specified by the following
register transfer statements:
a. T0: AR ← PC
Since only AR is connected to the address inputs of memory, it is necessary to
transfer the address from PC to AR.
b. T1: IR ← M[AR], PC ← PC+1
The instruction which is read from the memory is placed in the IR. At the same time
PC is incremented by one to prepare it for the address of the next instruction in the
program.
c. T2: D0,…,D7 ←IR(12-14), AR←IR(0-11), I←IR(15)
The operation code in IR is decoded. The indirect bit is transferred to flip-flop I and
the address part of the instruction is transferred to AR.
Determining the type of Instruction:
The timing signal that is active after the decoding is T3. During time T3, the control unit
determines the type of instruction that was just read from memory.
· Decoder output D7 is equal to 1 if the operation code is equal to binary 111. If D7=1, the
instruction must be a register reference or an input-output type.
o Control then inspects the value of the first bit of the instruction. Which is available in
the flip flop I.
If I=0 then the instruction is a register reference instruction.
If I=1 then the instruction must be an input-output instruction.
· If D7 is equal to 0 then the operation code must be one of the other seven values 000
through 110. So the instruction must be a memory reference instruction.
o If I=0 then the instruction is a memory reference instruction with direct address.
o If I=1 then the instruction is a memory reference instruction with an indirect address.
· If the instruction has an indirect address then it is necessary to read the effective address
from memory.
· When a memory reference instruction with direct address (I=0) is encountered then it is not
necessary to do anything since the effective address is already in
incremented so that the execution of the instruction can be continued with timing variable
T4.
· A register reference or input-output instruction can be executed, with the clock associated
with timing signal T3. After the instruction is executed, SC is cleared to 0 and control returns
to the fetch phase with T0=1.
Register reference instructions:
· Register-reference instructions are recognized by the control when D7=1 and I=0.
· These instructions use bits 0 through 11 of the instruction code to specify one of 12
instructions.
· The control functions and micro operations for the register reference instructions are:
· The halt HLT instruction clears start stop flip flop S and stops the sequence counter from
counting. To restore the operation of the computer, the start-stop flip-flop must be set
manually.
Memory reference instructions:
· The function of a memory reference instruction can be defined precisely by means of register
transfer notation.
· The decoded output Di for i=0,1,2,3,4,5 and 6 from the operation decoder belongs to
memory reference instructions.
· The effective address of the instruction is in the address register AR and was placed there
during timing signal
T2 when I=0
during T3 when I=1
· The execution of the memory-reference instruction starts with timing signal T4.
· The actual execution of the instruction in the bus system will require a sequence of micro
operations. This is because data stored in memory cannot be processed directly. The data
must be read from memory to a register where they can be operated on with logic circuits.
AND to AC:
· Performs AND logic operation on pairs of bits in AC and the memory word specified by the
effective address.
· The result of the operation is transferred to AC.
· The micro operations for this instruction are:
D0T4: DR ← M[AR]
D0T5: AC ← AC ^ DR, SC ← 0
· The control function for this instruction uses the operation decoder D0.
· Two timing signals are needed to execute the instruction.
o The clock transition associated with timing signal T4 transfers the operand from
memory into DR.
o The clock transition associated with T5 transfers to AC the result of the AND logic
operation between the contents of DR and AC.
ADD to AC:
· This instruction adds the contents of the memory word specified by the effective address.
· The sum is transferred into the AC Cout is transferred to the E flip flop.
· Two timing signals T4 & T5 are used with operation decoder D1
· The micro operations for this instruction are:
o D1T4: DR ← M[AR]
o D1T5: AC ← AC+DR, E ← Cout, SC← 0
LDA: Load to AC:
· This instruction transfers the memory word specified by the effective address to AC.
· The micro operations need to execute this instruction are
o D2T4: DR ← M[AR]
o D2T5: AC ← DR, SC← 0
· Since there is no direct path from the bus to the accumulator, we have to first read the
memory word into DR and then transfer the content of DR to AC.
STA: Store AC
· This instruction stores the contents of AC into the memory word specified by the effective
address.
· Since the output of AC is applied to the bus and the data input of memory is connected to the
bus, we can execute this instruction with one micro operation.
· The required micro operation is
o D3T4: M[AR] ← AC, SC ← 0
BUN: Branch Unconditionally
· This instruction transfers the control to the instruction specified by the effective address.
· The BUN instruction allows the programmer to specify an instruction out of sequence and
we say that the program branches unconditionally.
· This instruction is executed with one micro operation.
o D4T4: PC ← AR, SC ← 0
· The effective address from the AR is transferred through the common bus to PC. Resetting
SC to 0 transfers control to T0. The next instruction is then fetched and executed from the
memory address given by new value in PC.
BSA Branch & Save Return Address:
· This instruction is useful for branching to a portion of the program called a subroutine or
procedure.
· When executed, the BSA instruction
o stores the address of the next instruction in sequence into a memory location specified
by the effective address.
o The effective address plus one is then transferred to PC to serve as the address of the
first instruction in subroutine.
· The required micro operation for this instruction are:
D5T4: M[AR] ← PC, AR ← AR+1
D5T5: PC←AR, SC ←0
ISZ : Increment and skip if Zero
· This instruction increments the word specified by effective address and if the incremented
value is zero PC is incremented by 1.
· The programmer usually stores a negative number in 2’s complement in the memory word.
As this negative number is repeatedly incremented by one, it eventually reaches the value of
zero. At that time PC is incremented by one in order to skip the next instruction in the
program.
· The micro operations needed to execute this instruction is
D6T4: DR ← M[AR]
D6T5: DR←DR+1
D6T6: M[AR] ← DR, if (DR=0) then (PC ← PC+1), SC←0
Input-Output & Interrupt
Input-output configuration:
INPR and OUTR registers:
· The serial information from the Key board is shifted into the input register INPR.
· The serial information for the printer is stored in the output register OUTR.
· These two registers communicate with a communication interface serially and with the AC
in parallel.
Communication Interfaces:
· The transmitter interface receives the serial information from the keyboard and transmits it
to INPR.
· The receiver interface receives information from OUTR and sends it to the printer serially.
Flag Flip flops:
· The flag flip flops are control flip flops and are used to synchronize the timing rate
difference between the input/output device and the computer.
· There are two flag flip flops FGI and FGO.
o FGI :
Initially FGI is set to 0.
This flag bit is set to 1 when new information is available in the input device.
It is cleared to 0 when the information is accepted by the computer.
o FGO
Initially FGO is set to 1.
The computer checks FGO if it is 1, the information from AC is transferred in
parallel to OUTR and FGO is cleared.
The output device accepts the coded information, and when the information is
completed, it sets FGO to 1.
Computer will not load a new character into OUTR when FGO is 0.
Input – output instructions:
Program Interrupt:
Programmed control transfer:
· The computer keeps checking the flag bit, and when it is set, it initiates an information transfer.
· The difference of information flow rate between the computer and that of the input-output
device makes this type of transfer inefficient.
· The computer’s time is wasted while checking the flag.
Interrupt:
· An alternative to the programmed controlled procedure is to let the external device inform
the computer when it is ready for the transfer.
· This type of transfer uses the interrupt facility.
· While the computer is running a program, it does not check the flags. When a flag is set, the
computer is momentarily interrupted from the proceeding with the current program and is
informed of the fact that a flag has been set.
· The computer deviates momentarily from the current program and takes care of input or
output transfer.
· It then returns to the current program to continue what it was doing.
IEN: Interrupt enable flip flop
· The interrupt enable flip flop can be set and cleared with two instructions: ION and IOF.
· When IEN is set 1 the computer can be interrupted.
· When IEN is cleared to 0 with IOF instruction, the flags cannot interrupt the computer.
· The ION and IOF instructions provide the programmer with the capability of making a decision
as to whether or not to use the interrupt facility.
Interrupt flip flop:
· An interrupt flip flop R is included in the computer.
· When R=0 the computer goes through an instruction cycle.
· When R=1 the computer goes through an interrupt cycle.
· It is set during the execute phase of the instruction cycle if IEN=1 and either FGI or FGO is
set.
T0’T1’T2’(IEN)(FGI + FGO): R ← 1
· At the end of the execute phase, control checks the value of R, if R=1 it goes to an interrupt
cycle instead of an instruction cycle.
Interrupt Cycle:
· The interrupt cycle is a hardware implementation of a branch and save return address
operation.
· The interrupt cycle is initiated after the last execute phase if the interrupt flip-flop R is equal
to 1.o R flip flop is set to 1 if IEN=1 and either FGI or FGO are equal to 1.
o This can happen with any clock transition except when timing signals T0, T1, or T2 are
active.
o The condition for setting flip-flop R to 1 can be expressed with the following register
transfer statement:
T0’T1’T2’(IEN)(FGO+FGI): R ← 1
· The return address available in PC is stored in a specific location where it can be found later
when the program returns to the instruction at which it was interrupted.
o This location may be a processor register, a memory stack, or a specific memory
location.
o If memory location at address 0 is chosen as the place for storing the return address
then value in PC is stored at 0th location and control then inserts address 1 into PC
o IEN and R are cleared so that no more interruption can occur until the interrupt
request from the flag has been serviced.
· Modified fetch and decode phases of the instruction cycle:
Instead of using only timing signals T0, T1 and T2 we have to AND the three timing
signals with R’ so that the fetch and decode phases will be recognized from the three
control functions R’T0, R’T1 and R’T’2
· Register transfer statements for the interrupt cycle are:
· The flow chart for interrupt cycle is:
**********
Micro programmed Control
Control Memory:
Control Word: The control variables at any given time can be represented by a string of 1’s
and 0’s called a control word.
Hardwired control unit: When the control signals are generated by hardware using
conventional logic design techniques, the control unit is said to be hardwired.
Micro programmed control unit: Microprogramming is a second alternative for designing
the control unit of a digital computer. A control unit whose binary control variables are stored in
memory is called a micro programmed control unit.
Control Memory: A computer that employs a microprogrammed control unit will have two
separate memories: a main memory and a control memory. Main memory is available to the user for
storing the programs. A memory that is part of a control unit is referred to as a control memory.
Control Address Register: Control memory address register specifies the address of the
next microinstruction that is to be executed.
Control Data register: The control data register holds the microinstruction read from the
control memory. The microinstruction contains a control word that specifies one or more
microoperations for the data processor.
Sequencer: It is also called as next address generator. It determines the address sequence
that is read from control memory. Typical functions of microprogram sequencer are
· incrementing the control address register by one.
· loading into the control address register an address from control memory.
· transferring an external address.
· loading an initial address to start the control operations.
Advantage of Microprogrammed control: The main advantage of microprogrammed control is
the fact that once the hardware configuration is established, there should be no need for further
hardware or wiring changes. If we want to establish a different control sequencefor the system, all
we need to do is specify a different set of microinstructions for control memory. The hardware
configuration should not be changed for different operations. The only thing that must be changed is
the microprogram residing in control memory.
MICROPROGRAMMED CONTROL ORGANIZATION
Address sequencing:
· The address sequencing capabilities required in a control memory are:
1. incrementing of the control address register.
2. unconditional branch or conditional branch depending on the status bit conditions.
3. a mapping process from the bits of the instruction to ad address for control memory.
4. A facility for subroutine call and return.
· The microinstruction in control memory contains bits to initiate microoperations in computer
registers and other bits to specify the method by which the next address is obtained.
· The incrementer increments the content of the control address register by one,
· Branching is achieved by specifying the branch address in one of the fields of the
microinstruction. Conditional branching is obtained by using part of the microinstruction to
select a specific status bit in order to determine its condition.
· An external address is transferred into control memory via a mapping logic circuit.
· The return address for a subroutine is stored in a special register whose value is then used when
the microprogram wishes to return from the subroutine.
No comments:
Post a Comment